LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;

ENTITY registers IS
PORT (  Instr				: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
		R1, R2, R3, R4		: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
		Imed				: IN 	STD_LOGIC_VECTOR(7 DOWNTO 0);
		R1Out, R2Out		: OUT 	STD_LOGIC_VECTOR(7 DOWNTO 0));
END registers;

ARCHITECTURE behavior OF registers IS
	SIGNAL Op				: STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL IDX1, IDX2		: STD_LOGIC_VECTOR (1 DOWNTO 0);
	SIGNAL Aux				: STD_LOGIC_VECTOR (7 DOWNTO 0);
	
BEGIN
	Op <= Instr(7 DOWNTO 4);
	IDX1 <= Instr(3 DOWNTO 2);
	IDX2 <= Instr(1 DOWNTO 0);
	
	WITH IDX1 SELECT 
		R1Out	<=	R2 	WHEN "01",
					R3 	WHEN "10",
					R4 	WHEN "11",
					R1 	WHEN OTHERS;
	
	WITH IDX2 SELECT 
		Aux	<=	R2 	WHEN "01",
					R3 	WHEN "10",
					R4 	WHEN "11",
					R1 	WHEN OTHERS;
	
	WITH Op SELECT 
		R2Out	<=	Imed 	WHEN "1000",
					Imed 	WHEN "1011",
					Imed 	WHEN "1100",
					Imed 	WHEN "1101",
					Aux		WHEN OTHERS;
	
	

END behavior;
